This invention relates to differential receivers, and more particularly to latched fail-safe circuits for low-voltage differential signaling (LVDS) receivers.
Networking equipment and other electronic systems often transmit signals over cables. Although the cables may be only a few meters in length, a transmission-line effect degrades data quality and transmission rate. Large signal swings also increases electro-magnetic interference (EMI) and system noise. To send signals over these cables, special drivers and receivers have been developed.
The problems of the transmission-line effect have been mitigated with reduced voltage swings. Also, a pair of physical signals driven to opposite states are together used to transmit a single logical signal. Such differential signaling has been used with Emitter-coupled logic (ECL) for many years, and more recently in low-voltage differential signaling (LVDS) drivers and receivers.
LVDS drivers have a pair of outputs that are driven to opposite states. The two outputs are sent separately down the cable to the receiver, and at the far (receiver) end of the cable the lines are connected together by a terminating resistor. A current loop exists from one transmitter output, down the cable, through the terminating resistor, back up the cable to the other line""s transmitter output. A voltage drop occurs across the terminating resistor that is sensed by the receiver. However, the voltage difference across the terminating resistor between the two signals is small, perhaps only a few hundred millivolts. Sensitive receivers are needed to detect such a small voltage difference between the two signal lines.
In real-life systems, cables can become disconnected, such as by a network technician when networks are modified, or when a cable fails. The transmitter can also fail or be in a high-impedance output state. At these times, neither output line is driven. The voltage across the terminating resistor drops to near zero. Noise can be coupled into the cable from various sources, and this noise can be picked up by the receiver""s differential inputs. The output of the receiver can oscillate or enter an uncertain logic state, even though the differential receiver has common mode rejection. False triggering of receiver logic can occur.
To prevent such problems, fail-safe circuits have been employed. A simply fail-safe circuit uses resistors to connect the differential lines to power and ground. FIG. 1 shows a prior-art fail-safe circuit that connects the differential inputs to power and ground. Differential amplifier 10 receives a differential pair of input voltages V+, Vxe2x88x92, and amplifies the voltage difference between V+ and Vxe2x88x92 to generate the output VO. Output VO typically is a digital signal driven fully to power and ground.
Sometimes differential inputs V+, Vxe2x88x92 are not driven by the transmitter, such as when a cable to the transmitter is disconnected, shorted together, or broken, or the transmitter is in a high-impedance state or is non-operational. When not being driven, signals V+, Vxe2x88x92 can float to indeterminate voltages, and noise can be coupled in. To prevent output VO from being in an indeterminate state, resistors 12, 14 are added.
Pullup resistor 12 connects differential input V+ to power, while pull-down resistor 14 connects differential input Vxe2x88x92 to ground. Resistors 12, 14 have a high resistance, such as hundreds of K-Ohms or more, to minimize any voltage shift to V+, Vxe2x88x92 during normal operation when driven by the differential transmitter. However, when lines V+, Vxe2x88x92 are floating, the small current from pullup resistor 12 causes line V+ to rise to the power-supply voltage Vcc, while pull-down resistor 14 produces a small current to pull line Vxe2x88x92 down to ground. When V+, Vxe2x88x92 are floating, resistors 12, 14 ensure that the inputs of differential amplifier 10 are in the 1, 0 logical state, so that output VO is driven high by differential amplifier 10.
Resistors 12, 14 have some unwanted disadvantages. When the cable fails by shorting together the two signals V+, Vxe2x88x92, the fail-safe circuit does not function properly, since V+ and Vxe2x88x92 are shorted to the same voltage, and the small currents from resistors 12, 14 are not able to overcome the larger shorting current. Also, when a terminating resistor (not shown) is coupled between signals V+, Vxe2x88x92, this resistor conducts so much more current than resistors 12, 14, that V+, Vxe2x88x92 have the same voltage despite resistors 12, 14. Resistors 12, 14 have resistances of many K-Ohms, while the terminating resistor has a resistance of only 100 Ohms. Thus using pullup and pulldown resistors are not effective with LVDS receivers, which use 100-Ohm terminating resistors.
FIG. 2 shows another prior-art fail-safe circuit. When a 100-Ohm terminating resistor 22 connects V+ to Vxe2x88x92, the small current from resistors 12, 14 is insufficient to create enough voltage drop through terminating resistor 22. Series resistor 24 is added between V+ and the non-inverting input of differential amplifier 10, while series resistor 26 is added between Vxe2x88x92 and the inverting input of differential amplifier 10. The additional voltage drops through series resistors 24, 26 creates an additional voltage difference on the inputs to differential amplifier 10 when resistors 12, 14 supply the small current. This additional voltage difference on the input is enough to drive the VO output of differential amplifier 10 into a high state when a short occurs between V+ and Vxe2x88x92.
Unfortunately, the addition of series resistors 24, 26 increases the R-C delay of the cable driving the inputs of differential amplifier 10. This additional delay can be significant and is undesirable. Also, the resistance values of series resistors 24, 26 may introduce an unwanted offset voltage to the inputs of amplifier 10. s FIG. 3 shows a prior-art fail-safe circuit using an error-detection logic gate. When an open or a short occur on lines V+, Vxe2x88x92, pullup resistor 12 pulls signal V+ high, while pullup resistor 32 pulls signal Vxe2x88x92 high. Since both lines V+, Vxe2x88x92 are pulled high by resistors 12, 32, no current flows through terminating resistor 22.
AND gate 30 is coupled to the inverting and non-inverting inputs of differential amplifier 10. When an open or short occurs and resistors 12, 32 pull both V+ and Vxe2x88x92 high, AND gate 30 detects the high-high condition on its inputs and outputs a high to OR gate 40. OR gate 40 drives its VO output high, since one of its inputs is high. The state of the input from differential amplifier 10 does not matter. Thus any indeterminate state of the output from differential amplifier 10 is masked by OR gate 40.
A problem can occur during normal operation of differential amplifier 10. When inputs V+, Vxe2x88x92 have a high common-mode voltage, AND gate 30 can read the high voltages on V+ and Vxe2x88x92 as highs, even though enough of a voltage difference exists between V+ and Vxe2x88x92 to properly operate differential amplifier 10. For example, when a 3-volt power supply is used, AND gate 30 may detect all input voltages above 2.3 volts as a high voltage. Signals V+, Vxe2x88x92 may swing between 2.5 and 2.9 volts, having a high common-mode voltage of 2.7 volts. When V+ is 2.5 volts and Vxe2x88x92 is 2.9 volts, differential amplifier 10 detects and outputs a low during normal operation. However, AND gate 30 sees both inputs V+ and Vxe2x88x92 above its logic threshold of 2.3 volts, and outputs a high. OR gate 40 then outputs a high despite the low from differential amplifier 10. Thus the correct outputs signal from differential amplifier 10 is blocked by the false triggering of the fail-safe circuit. Note that this example used a raised threshold of 2.3 volts, compared with the normal logic threshold of Vcc/2 or 1.5 volts. The problem is much worse for a normal-threshold AND gate.
FIG. 4 is a prior-art differential receiver with a fail-safe circuit with a very high common-mode range. See U.S. Pat. No. 6,288,577 to Wong. A voltage across terminating resistor 22 is detected by differential amplifier 10. In normal operation, the lower input to NOR gate 48 is low, so that the output from differential amplifier 10 is passed through NOR gate 48 and inverted by inverter 52 to generate output VO.
The differential signals V+, Vxe2x88x92 are also applied to the inverting inputs of comparators 42, 44, respectively. The non-inverting inputs of comparators 42, 44 are driven by reference voltage VREF. Resistors 62, 64 form a voltage divider that generate VREF near Vcc, such as at 2.91 volts for a 3-volt Vcc.
One of V+, Vxe2x88x92 is low during normal operation. For example, when V+ is low, comparator 42 outputs a high, since VREF is above V+. When Vxe2x88x92 is low, comparator 44 outputs a high, since VREF is above Vxe2x88x92. However, when a cable or transmitter interruption or failure occurs, such as an open on V+, Vxe2x88x92, pullup resistors 12, 32 are able to pull signals V+ and Vxe2x88x92 up to Vcc, since no other currents are conducted from lines V+, Vxe2x88x92. When both of signals V+, Vxe2x88x92 rise above VREF, comparators 42, 44 both output lows to the inputs of NOR gate 46. NOR gate 46 then outputs a high to the lower input of NOR gate 48, causing NOR gate 48 to ignore its upper input from differential amplifier 10 and output a low to inverter 52, which drives VO high. This is the fail-safe condition, when an indeterminate output from differential amplifier 10 is blocked.
Although a very wide common-mode input range is tolerated, glitches and other transitory signals can disrupt operation and cause false triggering of the fail-safe condition. Inputs V+, Vxe2x88x92 are often tied to long lines which can act as antennas, picking up stray noise signals. What is desired is a noise-tolerant fail-safe circuit for a differential receiver.